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HI5813
August 1997
CMOS 3.3V, 25 Microsecond, 12-Bit, Sampling A/D Converter with Internal Track and Hold
Description
The HI5813 is a 3.3V, very low power, 12-bit, successive approximation analog-to-digital converter. It can operate from a single 3V to 6V supply and typically draws a maximum of 1.0mA (at 25oC) when operating at 3.3V. The HI5813 features a built-in track and hold. The conversion time is as low as 25s with a 3.3V supply. The twelve data outputs feature full high speed CMOS threestate bus driver capability, and are latched and held through a full conversion cycle. The output is user selectable: (i.e.) 12-bit , 8-bit (MSBs), and/or 4-bit (LSBs). A data ready flag and conversion start input complete the digital interface.
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Features
* Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 25s * Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . .40 KSPS * Built-In Track and Hold * Single Supply Voltage . . . . . . . . . . . . . . . . . . . . . . +3.3V * Maximum Power Consumption at 25oC. . . . . . . . 3.3mW
Applications
* Remote Low Power Data Acquisition Systems * Battery Operated Systems * Pen Based PC Handheld Scanners * DSP Modems * General Purpose DSP Front End * P Controlled Measurement Systems * PCMCIA Type II Compliant * PC Based Industrial Controls/DAQ Systems
Ordering Information
PART NUMBER HI5813JIP HI5813KIP HI5813JIB HI5813KIB HI5813JIJ HI5813KIJ INL (LSB) (MAX OVER TEMP.) 4.0 2.5 4.0 2.5 4.0 2.5 TEMP. RANGE (oC) PKG. NO. E24.3 E24.3 M24.3 M24.3
PACKAGE
-40 to 85 24 Ld PDIP -40 to 85 24 Ld PDIP -40 to 85 24 Ld SOIC -40 to 85 24 Ld SOIC
-40 to 85 24 Ld CERDIP F24.3 -40 to 85 24 Ld CERDIP F24.3
Pinout
HI5813 (PDIP, CERDIP, SOIC) TOP VIEW
DRDY (LSB) D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 VSS 1 2 3 4 5 6 7 8 9 10 11 12 24 VDD 23 OEL 22 CLK 21 STRT 20 VREF 19 VREF+ 18 VIN 17 VAA+ 16 VAA15 OEM 14 D11 (MSB) 13 D10
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File Number
3634.1
6-1802
HI5813 Functional Block Diagram
STRT VDD VSS VIN CONTROL AND TIMING 32C VREF+ OEM 16C D11 (MSB) 50 SUBSTRATE 8C D10 4C 2C VAA+ C VAA64C 63 32C D7 16C 8C 4C 2C C D3 C D2 D1 VREF D0 (LSB) OEL 12-BIT SUCCESSIVE APPROXIMATION REGISTER 12-BIT EDGE TRIGGERED "D" LATCHED D8 D9 CLOCK CLK DRDY TO INTERNAL LOGIC
D6
D5
D4
P1
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HI5813
Absolute Maximum Ratings
Supply Voltage VDD to VSS . . . . . . . . . . . . . . . . . . . . (VSS -0.5V) < VDD < +6.5V VAA+ to VAA-. . . . . . . . . . . . . . . . . . . . (VSS -0.5V) to (VSS +6.5V) VAA+ to VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V Analog and Reference Inputs VIN , VREF+, VREF- . . . . . . . . . (VSS -0.3V) < VINA < (VDD +0.3V) Digital I/O Pins . . . . . . . . . . . . . . (VSS -0.3V) < VI/O < (VDD +0.3V)
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 80 N/A SOIC Package . . . . . . . . . . . . . . . . . . . 75 N/A CERDIP Package . . . . . . . . . . . . . . . . 60 12 Maximum Junction Temperature PDIP and SOIC Packages. . . . . . . . . . . . . . . . . . . . . . . . . . 150oC CERDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Storage Temperature Range . . . . . . . . . .-65C to 150oC Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range PDIP, SOIC, and CERDIP Packages . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
VDD = VAA+ = VREF+ = 3.3V, VSS = VAA - = VREF - = GND, CLK = 600kHz (J suffix), CLK = 500kHz (K suffix), Unless Otherwise Specified 25oC
-40oC TO 85oC
MAX MIN MAX UNITS
PARAMETER ACCURACY Resolution Integral Linearity Error, INL (End Point) Differential Linearity Error, DNL J K J K Gain Error, FSE (Adjustable to Zero) Offset Error, VOS (Adjustable to Zero) DYNAMIC CHARACTERISTICS Signal to Noise Ratio, SINAD RMS Signal RMS Noise + Distortion Signal to Noise Ratio, SNR RMS Signal RMS Noise Total Harmonic Distortion, THD J K Spurious Free Dynamic Range, SFDR ANALOG INPUT Input Current, Dynamic Input Current, Static J K J K J K J K J K
TEST CONDITIONS
MIN
TYP
12 -
-
4.0 2.5 4.0 2.0 2.0 2.0 3.0 2.5
12 -
4.0 2.5 4.0 2.0 2.0 2.0 3.0 2.5
Bits LSB LSB LSB LSB LSB LSB LSB LSB
fS = 600kHz, fIN = 1kHz fS = 500kHz, fIN = 1kHz fS = 600kHz, fIN = 1kHz fS = 500kHz, fIN = 1kHz fS = 750kHz, fIN = 1kHz fS = 750kHz, fIN = 1kHz fS = 600kHz, fIN = 1kHz fS = 500kHz, fIN = 1kHz
-
61.5 63.9 63.2 65.1 -68.4 -70.8 69.0 71.8
-
-
-
dB dB dB dB dBc dBc dB dB
At VIN = VREF+, 0V Conversion Stopped
-
50 0.4
100 10
-
100 10
A A
6-1804
HI5813
Electrical Specifications
VDD = VAA+ = VREF+ = 3.3V, VSS = VAA - = VREF - = GND, CLK = 600kHz (J suffix), CLK = 500kHz (K suffix), Unless Otherwise Specified (Continued) 25oC PARAMETER Input Bandwidth -3dB Reference Input Current Input Series Resistance, RS Input Capacitance, CSAMPLE Input Capacitance, CHOLD DIGITAL INPUTS OEL, OEM, STRT High-Level Input Voltage, VIH Low-Level Input Voltage, VIL Input Leakage Current, IIL Input Capacitance, CIN DIGITAL OUTPUTS High-Level Output Voltage, VOH Low-Level Output Voltage, VOL Three-State Leakage, IOZ Output Capacitance, COUT TIMING Conversion Time (tCONV + tACQ) (Includes Acquisition Time) Clock Frequency Clock Pulse Width, tLOW, tHIGH Aperture Delay, tDAPR Clock to Data Ready Delay, tD1DRDY Clock to Data Ready Delay, tD2DRDY Start Removal Time, tRSTRT Start Setup Time, tSUSTRT Start Pulse Width, tWSTRT Start to Data Ready Delay, tD3 DRDY Output Enable Delay, tEN Output Disabled Delay, tDIS POWER SUPPLY CHARACTERISTICS Supply Current, IDD + IAA NOTE: 2. Parameter guaranteed by design or characterization, not production tested. 0.5 1 2.5 mA J K (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) 25 30 0.05 100 75 85 35 180 180 30 60 15 110 65 95 0.75 50 210 220 25 130 75 110 25 30 0.05 100 75 30 0.75 70 240 250 25 160 80 130 s s MHz ns ns ns ns ns ns ns ns ns ns ISOURCE = -400A ISINK = 1.6mA Except DRDY, VOUT = 0V, 3.3V Except DRDY 2.6 20 0.4 10 2.6 0.4 10 V V A pF Except CLK, VIN = 0V, 5V 2.4 10 0.8 10 2.4 0.8 10 V V A pF In Series with Input CSAMPLE During Sample State During Hold State TEST CONDITIONS MIN TYP 1 160 420 380 20 MAX
-40oC TO 85oC
MIN MAX UNITS MHz A pF pF
6-1805
HI5813 Timing Diagrams
1 2 3 4 5 - 14 15 1 2 3
CLK tD1DRDY tLOW tHIGH STRT tD2DRDY DRDY
D0 - D11
DATA N - 1
DATA N
VIN
HOLD N TRACK N TRACK N + 1
OEL = OEM = VSS
FIGURE 1. CONTINUOUS CONVERSION MODE
15 CLK
1
2
2
2
3
4
5
tRSTRT
tSUSTRT tWSTRT
STRT tD3DRDY
DRDY
HOLD VIN TRACK
HOLD
FIGURE 2. SINGLE SHOT MODE
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HI5813 Timing Diagrams
OEL OR OEM tEN 90% 50% D0 - D3 OR D4 - D11 HIGH IMPEDANCE TO HIGH HIGH IMPEDANCE TO LOW TO OUTPUT PIN 50% 10% -1.6mA +2.1V 50pF tDIS
(Continued)
1.6mA
FIGURE 3A. FIGURE 3. OUTPUT ENABLE/DISABLE TIMING DIAGRAM
FIGURE 3B.
1.6mA
+2.1V 50pF
-400A
AMPLITUDE (dB)
INPUT FREQUENCY = 1kHz SAMPLING RATE = 33kHz SNR = 65.55dB SINAD = 64.18dB EFFECTIVE BITS = 10.37 THD = -70.02dBc PEAK NOISE = -70.9dB SFDR = 71.1dB
FREQUENCY
FIGURE 4. GENERAL TIMING LOAD CIRCUIT
FIGURE 5. FFT SPECTRUM
Typical Performance Curves
4.00 3.60 3.20 2.80 2.40 INL (LSBs) 2.00 CLK = 500kHz 1.60 1.20 0.80 0.40 0.00 -50 -40 -30 -20 -10 0 10 20 30 40 50 TEMPERATURE (oC) 60 70 80 90 DNL ERROR (LSBs) VDD = VAA+ = VREF+ = 3.3V CLK = 600kHz 4.00 3.60 3.20 2.80 2.40 2.00 1.60 1.20 0.80 0.40 0.0 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 CLK = 500kHz CLK = 600kHz VDD = VAA+ = VREF+ = 3.3V
TEMPERATURE (oC)
FIGURE 6. INL vs TEMPERATURE
FIGURE 7. DNL vs TEMPERATURE
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HI5813 Typical Performance Curves
1.20 VDD = VAA+ = VREF+ = 3.3V 1.10 VOS ERROR (LSBs) 1.00 0.90 0.80 CLK = 500kHz 0.70 0.60 0.50 -50 -40 -30 -20 -10 CLK = 600kHz FSE (LSBs) 0.00 -0.10 -0.20 -0.30 CLK = 600kHz -0.40 -0.50 -0.60 -0.70 -0.80 -0.90 0 10 20 30 40 50 60 70 80 90 -1.00 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (oC) VDD = VAA+ = VREF+ = 3.3V CLK = 500kHz
TEMPERATURE (oC)
FIGURE 8. OFFSET ERROR vs TEMPERATURE
2.00 SUPPLY CURRENT, IDD (mA) 1.80 1.60 1.40 1.20 1.00 0.80 0.60 CLK = 500kHz 0.5 0 10 20 30 40 50 60 70 80 90 VDD = VAA+ = VREF+ = 3.3V 2.5 DNL ERROR (LSBs) 3.0
FIGURE 9. FULL SCALE ERROR vs TEMPERATURE
VDD = VAA+ = VREF+
2.0
1.5 CLK = 600kHz 1.0 CLK = 500kHz
0.40 -50 -40 -30 -20 -10
3.0
3.1
3.2
3.3
3.4
3.5
3.6
TEMPERATURE (oC)
SUPPLY VOLTAGE (V)
FIGURE 10. SUPPLY CURRENT vs TEMPERATURE
FIGURE 11. DNL vs SUPPLY VOLTAGE
Pin Descriptions
PIN # 1 NAME DRDY DESCRIPTION Output flag signifying new data is available. Goes high at end of clock period 15. Goes low when new conversion is started. Bit 0 (Least Significant Bit, LSB). Bit 1. Bit 2. Bit 3. Bit 4. Bit 5. Bit 6. Bit 7. Bit 8. Bit 9. Digital Ground, (0V). Bit 10. 22 23 24 CLK OEL VDD 21 STRT PIN # 14 15 16 17 18 19 20 NAME D11 OEM VAAVAA+ VIN VREF+ VREFDESCRIPTION Bit 11 (Most significant bit, MSB) Three-State enable for D4-D11. Active Low Input. Analog Ground, (0V). Analog Positive Supply. (+3.3V) (See text.) Analog Input. Reference Voltage Positive Input, sets 4095 code end of input range. Reference Voltage Negative Input, sets 0 code end of input range. Start Conversion Input active low, recognized after end of clock period 15. CLK Input. Conversion functions are synchronized to positive going edge. (See text) Three-State Enable for D0 - D3. Active low input. Digital Positive Supply (+3.3V).
2 3 4 5 6 7 8 9 10 11 12 13
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 VSS D10
6-1808
HI5813 Theory of Operation
HI5813 is a CMOS 12-Bit, Analog-to-Digital Converter that uses capacitor charge balancing to successively approximate the analog input. A binary weighted capacitor network forms the A/D heart of the device. See the block diagram for the HI5813. The capacitor network has a common node which is connected to a comparator. The second terminal of each capacitor is individually switchable to the input, VREF+ or VREF -. During the first three clock periods of a conversion cycle, the switchable end of every capacitor is connected to the input and the comparator is being auto balanced at the capacitor common node. During the fourth period, all capacitors are disconnected from the input; the one representing the MSB (D11) is connected to the VREF+ terminal; and the remaining capacitors to VREF -. The capacitor common node, after the charges balance out, will indicate whether the input was above 1/2 of (VREF+ - VREF -). At the end of the fourth period, the comparator output is stored and the MSB capacitor is either left connected to VREF+ (if the comparator was high) or returned to VREF -. This allows the next comparison to be at either 3/4 or 1/4 of (VREF+ - VREF -). At the end of periods 5 through 14, capacitors representing D10 through D1 are tested, the result stored, and each capacitor either left at VREF+ or at VREF -. At the end of the 15th period, when the LSB (D0) capacitor is tested, (D0) and all the previous results are shifted to the output registers and drivers. The capacitors are reconnected to the input, the comparator returns to the balance state, and the data ready output goes active. The conversion cycle is now complete. Analog Input The analog input pin is a predominately capacitive load that changes between the track and hold periods of the conversion cycle. During hold, clock period 4 through 15, the input loading is leakage and stray capacitance, typically less than 5A and 20pF. At the start of input tracking, clock period 1, some charge is dumped back to the input pin. The input source must have low enough impedance to dissipate the current spike by the end of the tracking period. The amount of charge is dependent on supply and input voltages. The average current is also proportional to clock frequency. As long as these current spikes settle completely by end of the signal acquisition period, converter accuracy will be preserved. The analog input is tracked for 3 clock cycles. With a clock of 500kHz the track period is 6s. A simplified analog input model is presented in Figure 12. During tracking, the A/D input (VIN) typically appears as a 380pF capacitor being charged through a 420 internal switch resistance. The time constant is 160ns. To charge this capacitor from an external "zero " source to 0.5 LSB (1/8192), the charging time must be at least 9 time constants or 1.4s. The maximum source impedance (RSOURCE Max) for a 6s acquisition time settling to within 0.5 LSB is 1.3k. If the clock frequency was slower, or the converter was not restarted immediately (causing a longer sample time), a higher source impedance could be tolerated.
VIN RSW 420 CSAMPLE 380pF RSOURCE
-tACQ - RSW RSOURCE (MAX) = CSAMPLE ln [2-(N + 1)] FIGURE 12. ANALOG INPUT MODEL IN TRACK MODE
Reference Input The reference input VREF+ should be driven from a low impedance source and be well decoupled. Current spikes are generated on the reference pin during each bit test of the successive approximation part of the conversion cycle as the charge balancing capacitors are switched between VREF - and VREF+ (clock periods 5 - 14). These current spikes must settle completely during each bit test of the conversion to not degrade the accuracy of the converter. Therefore VREF+ and VREF - should be well bypassed. Reference input VREF - is normally connected directly to the analog ground plane. If VREF - is biased for nulling the converters offset it must be stable during the conversion cycle. Full Scale and Offset Adjustment In many applications the accuracy of the HI5813 would be sufficient without any adjustments. In applications where accuracy is of utmost importance full scale and offset errors may be adjusted to zero. The VREF+ and VREF - pins reference the two ends of the analog input range and may be used for offset and full scale adjustments. In a typical system the VREF - might be returned to a clean ground, and the offset adjustment done on an input amplifier. VREF+ would then be adjusted to null out the full scale error. When this is not possible, the VREF input can be adjusted to null the offset error, however, VREF must be well decoupled. Full scale and offset error can also be adjusted to zero in the signal conditioning amplifier driving the analog input (VIN). Control Signal The HI5813 may be synchronized from an external source by using the STRT (Start Conversion) input to initiate conversion, or if STRT is tied low, may be allowed to free run. Each conversion cycle takes 15 clock periods. The input is tracked from clock period 1 through period 3, then disconnected as the successive approximation takes place. After the start of the next period 1 (specified by tD data), the output is updated.
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HI5813
The DRDY (Data Ready) status output goes high (specified by tD1DRDY) after the start of clock period 1, and returns low (specified by tD2DRDY) after the start of clock period 2. The 12 data bits are available in parallel on three-state bus driver outputs. When low, the OEM input enables the most significant byte (D4 through D11) while the OEL input enables the four least significant bits (D0 - D3). tEN and tDIS specify the output enable and disable times. If the output data is to be latched externally, either the trailing edge of data ready or the next falling edge of the clock after data ready goes high can be used. Figure 2 shows operation of the HI5813 when the STRT pin is used to initate a conversion. If STRT is taken high at least tRSTRT before clock period 1 and is not reapplied during that period, the converter will stay in the track mode and the DRDY output will remain high. A low signal applied to STRT will bring the DRDY flag low and the conversion will continue with clock period 3 on the first positive going clock edge that meets the tSUSTRT setup time. Clock The clock used to drive the HI5813 can range in frequency from 50kHz up to 750kHz. All converter functions are synchronized with the rising edge of the clock signal. The clock can be shut off only during the sample (track) portion of the conversion cycle. At other times it must be above the minimum frequency shown in the specifications. In the above two cases, a further restriction applies in that the clock should not be shut off during the third sample period for more than 1ms. This might cause an internal charge pump voltage to decay. If the clock is shut off during the conversion time (clock cycles 4 through 15) of the A/D, the output might be invalid due to balancing capacitor droop. The clock must also meet the minimum tLOW and tHIGH times shown in the specifications. A violation may cause an internal miscount and invalidate the results. Power Supplies and Grounding VDD and VSS are the digital supply pins: they power all internal logic and the output drivers. Because the output drivers can cause fast current spikes in the VDD and VSS lines, VSS should have a low impedance path to digital ground and VDD should be well bypassed. Except for VAA+, which is a substrate connection to VDD , all pins have protection diodes connected to VDD and VSS . Input transients above VDD or below VSS will get steered to the digital supplies. The VAA+ and VAA- terminals supply the charge balancing comparator only. Because the comparator is autobalanced between conversions, it has good low frequency supply rejection. It does not reject well at high frequencies however; VAA- should be returned to a clean analog ground and VAA+ should be RC decoupled from the digital supply as shown in Figure 13. There is approximately 50 of substrate impedance between VDD and VAA+. This can be used, for example, as part of a low pass RC filter to attenuate switching supply ENOB = Total Harmonic Distortion The total harmonic distortion (THD) is the ratio of the RMS sum of the second through sixth harmonic components to the fundamental RMS signal for a specified input and sampling frequency. THD = 10 Log Total Harmonic Power (2nd - 6th Harmonic) Sinewave Signal Power noise. A 10F capacitor from VAA+ to ground would attenuate 30kHz noise by approximately 40dB. Note that back to back diodes should be placed from VDD to VAA+ to handle supply to capacitor turn-on or turn-off current spikes. Dynamic Performance Fast Fourier Transform (FFT) techniques are used to evaluate the dynamic performance of the A/D. A low distortion sine wave is applied to the input of the A/D converter. The input is sampled by the A/D and its output stored in RAM. The data is than transformed into the frequency domain with a 4096 point FFT and analyzed to evaluate the converters dynamic performance such as SNR and THD. See typical performance characteristics. Signal-To-Noise Ratio The signal to noise ratio (SNR) is the measured RMS signal to RMS sum of noise at a specified input and sampling frequency. The noise is the RMS sum of all except the fundamental and the first five harmonic signals. The SNR is dependent on the number of quantization levels used in the converter. The theoretical SNR for an N-bit converter with no differential or integral linearity error is: SNR = (6.02N + 1.76)dB. For an ideal 12-bit converter the SNR is 74dB. Differential and integral linearity errors will degrade SNR: SNR = 10 Log Sinewave Signal Power Total Noise Power
Signal-To-Noise + Distortion Ratio SINAD is the measured RMS signal to RMS sum of noise plus harmonic power and is expressed by the following: SINAD = 10 Log Sinewave Signal Power Noise + Harmonic Power (2nd - 6th)
Effective Number of Bits The effective number of bits (ENOB) is derived from the SINAD data: SINAD - 1.76 6.02
Spurious-Free Dynamic Range The spurious-free dynamic range (SFDR) is the ratio of the fundamental RMS amplitude to the rms amplitude of the next largest spur or spectral component. If the harmonics are buried in the noise floor it is the largest peak. SFDR = 10 Log Sinewave Signal Power Highest Spurious Signal Power
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HI5813
TABLE 2. CODE TABLE INPUT VOLTAGE VREF+ = 3.3V VREF - = 0.0V (V) 3.2992 3.2984 2.4750 1.6500 0.8250 0.00080566 0 BINARY OUTPUT CODE MSB DECIMAL COUNT 4095 4094 3072 2048 1024 1 0 D11 1 1 1 1 0 0 0 D10 1 1 1 0 1 0 0 D9 1 1 0 0 0 0 0 D8 1 1 0 0 0 0 0 D7 1 1 0 0 0 0 0 D6 1 1 0 0 0 0 0 D5 1 1 0 0 0 0 0 D4 1 1 0 0 0 0 0 D3 1 1 0 0 0 0 0 D2 1 1 0 0 0 0 0 D1 1 1 0 0 0 0 0 LSB D0 1 0 0 0 0 1 0
CODE DESCRIPTION Full Scale (FS) FS - 1 LSB
3/ FS 4 1/ FS 2 1/ FS 4
1 LSB Zero
The voltages listed above represent the ideal lower transition of each output code shown as a function of the reference voltage.
+3.3V
0.1F 10F 0.1F 0.01F VAA+ VDD D11 . . . D0 DRDY OEM ANALOG INPUT VIN OEL STRT CLK VREF VAAVSS
4.7F
OUTPUT DATA
VREF+
500kHz CLOCK
FIGURE 13. GROUND AND SUPPLY DECOUPLING
6-1811
HI5813 Die Characteristics
DIE DIMENSIONS: 3200m x 3940m METALLIZATION: Type: AlSi Thickness: 11kA 1kA PASSIVATION: Type: PSG Thickness: 13kA 2.5kA WORST CASE CURRENT DENSITY: 1.84 x 105 A/cm2
Metallization Mask Layout
HI5813
D1 D0 (LSB) DRDY VDD OEL
CLK D2 STRT D3 VREF -
D4
D5
D6
VREF +
D7
VIN D8 VAA + VAA -
D9
VSS
D10
D11 (MSB)
OEM
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